Soliton 數位協定自動化驗證方案 - I3C
Soliton Technologies 是一家專注於數位協定驗證解決方案的公司，特別是在 MIPI I3C® 協定方面。其 I3C Protocol Validation Suite 利用 NI 的 PXI 平台 ( PXIe-6570 / 6571 )，提供自動化的功能、時序和電氣符合性測試，涵蓋 SDR、HDR-DDR 模式、動態位址分配、In-Band Interrupts 等功能，並支援錯誤注入與容錯測試，協助半導體公司快速驗證產品的協定相容性。
Soliton 數位協定驗證方案
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Device Read/Write
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Interrupts
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Device Addressing, etc.
Soliton 數位協定驗證方案軟體介面
I3C 協定簡介
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MIPI I3C® 是一種可擴展的中速公用與控制匯流排，廣泛用於手機、穿戴式裝置與汽車電子
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目標在於簡化周邊元件與應用處理器的連接，提升整合效率並降低成本。
驗證挑戰
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隨協定與產品設計日益複雜，傳統手動驗證方法耗時費力，延後產品上市時程。
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確保協定相容性與異常狀況容錯能力成為驗證關鍵。
Soliton I3C Validation Suite 優勢
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基於 NI PXI 平台，提供自動化、即插即用的驗證工具。
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支援時序與電氣規範驗證，並可測試容錯與異常回復能力。
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自動產生完整測試報告，提升除錯與驗證效率。
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用戶經驗顯示，可將驗證時間從數週縮短至數天。
Soliton I3C Validation Suite 組成
Soliton 的 I3C Validation Suite 是一套現成的驗證工具，搭載 NI PXI 平台，協助驗證裝置是否符合 MIPI I3C® 協定的時序與電氣規格。其組成包含以下元件：
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NI PXIe 657x ─ 數位模式產生卡，搭配 PXIe 機箱架構
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Soliton PVS 轉接板（Interposer Board）
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示波器 ─ 執行電壓量測
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Soliton I3C Validation Suite 軟體 ─ 支援 Windows 作業系統 (Windows 10)
MIPI I3C Protocal - Functional Coverage
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I3C SDR Mode (15 MHz)
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I3C HDR-DDR Mode (15 MHz)
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Legacy I2C Mode (5 MHz)
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Register Write (Legacy I2C/SDR/HDR)
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Register Read (Legacy I2C/SDR/HDR)
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Write N Bytes (Legacy I2C/SDR/HDR)
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Read N Bytes (Legacy I2C/SDR/HDR)
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Write N - Read N Bytes (Combined Format) (Legacy I2C/SDR/HDR)
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Hot Join Funtional Test
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IBI Funtional Test
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IBI Interrupt Spacing Test
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Clock Stalling
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SDR and HDR DDR CCC Commands
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Compliance Test Suite (CTS)
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Dynamic/Statics Addressing
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Direct and Broadcast CCC Commands
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Start / Stop Coditions
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Address Header and Transition Bit
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HDR DDR Restart and Exit Patterns
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Target Reset Patterns
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Group Target Addressing
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Induce SDR Errors (S0-S5)
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Induce HDR / DDR Errors
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Skip Start / Stop / Repeated Start
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Skip HDR Restarts / HDR Exit
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Add Clock from Address / data bytes
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Skip Clock from Address / data bytes
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Induce Parity / Preamble Errors
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Induce Error in CRCS Calculation
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Any Custom Faults in SDR / HDR DRR Transactions and can Check if the Slave is able to Recover from the Faults
MIPI I3C Protocal - Parametric Coverage
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fSCL - SCL Clock Frequency
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tSU - STA - Setup Time for Repeated Start
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tHD - STA - Hold Time for a (Repeated ) Start
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tLow, tDIG_L - SCL Clock Low Period
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tHIGH, tDIG_H - SCL Clock High Period
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tSU - DAT - Data Setup Time
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tHD - DAT - Data Hold Time
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trCL - SCL Single Rise Time
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tfCL - SCL Single Fall Time
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trDA - SDA Single Rise Time
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tfDA - SDA Single Fall Time
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tSU_STO - Setup Time for Stop
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tBUF - Bus Free Time Between a Stop and a Start
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tSPIKE - Pluse Width of Spikes to Supress
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tLOW_OD, tDIG_OD_L-Low Period of SCL Clock
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tHIGH_OD, tDIG_OD_H-High Period of SCL Clock
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tfDA_OD - Fall Time of SDA Signal
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tSU_OD - Data Setup Time During Open - Drain Mode
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tCAS - Clock after Start Condition
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tCBP - Clock before Stop Condition
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tAVAL - Bus Available Condition
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tIDLE - Bud Idle Condition
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fSCL - SCL Clock Frequency
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tLOW_PP, tDIG_L - SCL Clock Low Period
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tHIGH_PP, tDIG_H - SCL Clock High Period
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tSCO - Clock in to Data out for Slave
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tCR - SCL Clocl Rise Time
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tCF - SCL Clocl Fall Time
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tHD_PP - SDA Signal Data Hold in Push - Pull Mode
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tSU_PP - SDA Signal Data Setup in Push - Pull Mode
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tCASr - Clock after Repteated Start Condition
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tCBSr - Clock before Repteated Start Condition
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VIL - Low-Level Input Voltage
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VIH - High-Level Input Voltage
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Vhys - Schmitt Trigger Input Hysteresis
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VOL - Output Low Level
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VOH - Output High Level